Electrochemical etching of semiconductor materials in order to form porous semiconductor material structures is becoming well known and commonly practiced. A method for etching macropores (i.e., straight pores with diameters in the 100 nm to 100 μm range) in n-doped silicon was described in 1990 [V. Lehmann, H Foell, J. Elecrochem. Soc., 137 (1990), p. 653]. Since that time, such methods have been expanded to p-doped silicon and other semiconductor materials. Processes for the etching of mesoporous silicon (pore diameters in the 5 nm to 100 nm range) have been developed to various degrees as well.
Porous semiconductor technology has found applications in optics, micromachining, capacitors and Silicon-on-Insulator (SOI) fabrication, to name a few. However, current art methods of electrochemical etching of semiconductors are still not entirely satisfactory for at least some applications. Electrochemical dissolution of semiconductors is a complex process, strongly dependent on many parameters, e.g. current density, semiconductor wafer doping type and doping density, electrolyte composition, illumination intensity (if used) and/or temperature, to name a few. Many of the parameters change during the anodization process itself, especially in the case of etching very high aspect ratio pores (length to diameter of 50 to 200), which is often the case. There exist physical constraints that lead to the natural modification of the electrochemical etching parameters during the electrochemical etching process. These effects include changing pore growth parameters, including speed of the pore tips into the wafer, porosity (ratio of pore cross sectional area to total area), and others. From another point of view, many applications for porous semiconductor materials require tight control over the porous structure throughout the whole depth of the porous part of semiconductor wafer. In order to fulfill such demanding requirements, it has been found that closed-loop control utilizing active feedback of the etch parameters must be implemented in the electrochemical etching process. In other words, certain parameters of the electrochemical system need to be actively monitored, and some of the electrochemical etching parameters need to be actively adjusted according to the results of such a monitoring.
Information about manufacturing straight pore Macroporous Silicon (MPSi) arrays can be found in U.S. Pat. No. 5,262,021, issued to V. Lehmann et al. Nov. 16, 1993 (which claims priority to Fed. Rep. Of Germany Patent # 4202454, issued Jan. 29, 1992), in which a method for the formation of free-standing macropore arrays from an n-doped Si wafer is disclosed. Macroporous silicon layers with modulated pore diameters throughout the pore depth is disclosed in, for example, [U.S. Pat. No. 5,987,208 issued to U. Gruning and V. Lehmann et al. Nov. 16, 1999] or [J. Schilling et al., Appl. Phys. Lett. V 78, N.9, February 2001]. As disclosed in this prior art, changes of the etching parameters over the etching time severely limit the maximum obtainable thickness of the useful MPSi layer.
There are also several disclosures related to the method of manufacture of macroporous structures with controlled positions of the pores. One disclosure is U.S. Pat. No. 4,874,484 issued to H. Föll and V. Lehmann, issued Oct. 17, 1989 (which claims priority to Fed. Rep. Of Germany Patent # 3717851 dated May 27, 1987). This patent describes a method of fabricating MPSi arrays from n-doped, (100)-oriented silicon wafers in HF-based aqueous electrolytes (i.e., electrolytes based on hydrofluoric acid diluted with water) under the presence of backside illumination, and also describes a method of controlling the position of macropores through formation of etch-pits. Etch pits are typically, but not exclusively, pyramid-shaped openings formed on the silicon or other semiconductor surface that can be formed through mask openings upon exposure to anisotropic chemical etchants. In addition, the use of wetting agents (such as formaldehyde) and controlling the pore profile through chronologically-varying applied electrical potentials are disclosed. A detailed review of the various aspects of MPSi formation can be found in H. Föll et. al, Mat. Sci. Eng. R 39 (2002), pp. 93-141.
In addition to silicon, macropores have been produced in other types of semiconductor and ceramic materials. Macropores obtained in n-type GaAs by electrochemical etching in acidic electrolytes (aqueous HCl-based), were reported by, for example, D. J. Lockwood et al., Physica E, 4, p. 102 (1999) and S. Langa et al., Appl. Phys. Lett. 78(8), pp. 1074-1076, (2001). Macropores obtained in n-type GaP by electrochemical etching were reported by B. H. Erne et al., Adv. Mater. 7, p. 739 (1995). Macropore formation during the electrochemical etching of n-type InP (in aqueous and organic solutions of HCl and mixtures of HCl and H2SO4) was reported by P. A. Kohl et al., J. Electrochem. Soc., 130, p. 228 (1983) and more recently by P. Schmuki et al., Physica Status Solidi A, 182 (1), pp. 51-61, (2000); S. Langa et al., J. Electrochem. Soc. Lett., 3 (11), p. 514, (2000). Macroporous GaN formation during electrochemical etching was reported by J. v. d. Lagemaat, Utrecht (1998). Macropore formation during electrochemical etching of Ge was reported by S. Langa et al., Phys. Stat. Sol. (A), 195 (3), R4-R6 (2003). Reviews of macropore formation in III-V semiconductors can be found in H. Föll et al., Phys. Stat. Sol. A, 197 (1), p. 64, (2003); M. Christophersen et al., Phys. Stat. Sol. A, 197 (1), p. 197, (2003), and H. Föll et al., Adv. Materials, Review, 2003, 15, pp. 183-198, (2003).
Although etching mesoporous silicon layers has been known for many years, the interest in etching mesoporous structures with porosity modifications across the mesoporous layer depth arose only recently after the discovery of the possibility of the use of such material for optical filters (see, for example, G. Vincent, “Optical-properties of porous silicon superlattices”, Appl. Phys. Lett., 64 (18): 2367-2369, May 1994; foreign Application priority Jun. 14, 1993 [DE], 43 19 413.3; and U.S. Pat. No. 6,130,748 (issued Oct. 10, 2000 to M. Krueger et al., claiming priority to DE Patent 196 08 428 issued Mar. 5, 1996). Generally, mesoporous silicon is porous silicon material with pores in the range of 5 nm to 100 nm embedded in the silicon host. It can be obtained by electrochemically etching, in HF-containing electrolytes, highly doped silicon wafers (n-type or p-type) with resistivities typically in the range of 0.001-0.1Ω cm. A multilayer structure with different porosities in different layers can easily be obtained by temporal variations of the electrochemical etching parameters during the etching process. The most popular parameter used to control the porosity is the anodization current density. Differing porosities in different layers yield different refractive indices according to the porosity, so interference filters can be realized using this technique. Although in the majority of disclosures thus far, the depth of mesoporous layers was low enough (and, consequently, the time of the processing was fast enough) to develop the problems with changing of the electrochemical etching conditions, recently it was demonstrated that mesoporous multilayers can be etched several hundreds microns thick and can find applications in mid and far infrared filters [M. Christophersen, V. Kochergin, P. R. Swinehart, “Porous Silicon filters for mid-to-far IR range”, SPIE 49th Annual Meeting, Denver, Colo., USA August 2004. Proc. SPIE Vol. 5524, p. 158-168, Novel Optical Systems Design and Optimization VII; Jose M. Sasian, R. John Koshel, Paul K. Manhart, Richard C. Juergens; Eds. October 2004]. During etching of such a deep mesoporous structure, strict control of porosity throughout the layer depth requires active adjustment of the electrochemical etching parameters, as in the case of macroporous silicon described above.
Several attempts to implement open-loop control (i.e., characterizing the electrochemical etching parameters and mathematically adjusting the process parameters with time, but with no real time parameter input) have been made recently. For example, in a number of publications ([S. Langa, J. Carstensen, M. Christophersen, and H. Föll, I. M. Tiginyanu, Self Induced Voltage Oscillations during Anodic Etching of n-InP and Possible Applications for Three-dimensional Micro Structures, Electrochem. Solid-State Lett., 4, G50 (2001)], [J. C. Claussen, J. Carstensen, M. Christophersen, S. Langa, H. Föll, Oscillations, synchronization, and open-loop control in electrochemical semiconductor pore etching, Frühjahrstagung der Deutschen Physikalischen Gesellschaft, March 11-15, Regensburg, Germany], [S. Langa et al., Phys. Stat. Sol. A, 197 (1), pp. 186-191 (2003)]) it was observed that correlated voltage oscillations in certain macroporous systems during electrochemical processes take place, and the frequency of these oscillations was proposed as an open-loop control parameter. Particularly, it was disclosed that low frequency (below 100 Hz, in most cases below 10 Hz) voltage oscillations during electrochemical etching of p-doped Si, n-doped InP and GaP semiconductor materials, takes place during constant current electrochemical etching conditions, each with some characteristic oscillation frequency that is strongly dependent on the electrochemical etching parameters and strongly shifts with the time of electrochemical etching.
Another method of monitoring the anodization parameters during electrochemical etching of semiconductor materials has been disclosed in German patent DE0010011253A1 [Kontrollierte Porenätzung in Halbleitern, J. Carstensen, H. Föll, M. Christophersen, G. Hasse Veröffentlichungsnummer DE0010011253A1, Veröffentlichungsdatum Sep. 13, 2001]. In this patent it was proposed to use so-called impedance spectroscopy (i.e., to measure the complex resistance of the system at some frequency in the kHz range) to monitor the electrochemical etching. The idea was supported by an experimental plot, clearly indicating some changes in the real part of the impedance at a 2.6 kHz frequency.
From still another point of view, it is known to those skilled in the art that the electrochemical etching rate and the macropore cross-sections, for n-doped silicon etching in aqueous electrolyte and under the back-side illumination conditions, are both functions of a parameter designated as Jps, which is the value of the current density at the so-called “porous silicon peak” on the current-voltage (IV) curve. It was also noticed that the voltage and current positions of Jps are not constant during the electrochemical etching of deep macroporous layers. However, no closed-loop control over the electrochemical etching parameters has been found yet, based on these findings.
To summarize, despite the fact that some knowledge of electrochemical semiconductor etching processes has been developed over the last decade, a practical scheme (or schemes) for active feedback during electrochemical etching is needed in order to enhance the quality of porous semiconductor structures in order to meet the demands of certain applications.
The present exemplary illustrative non-limiting implementations provide a number of closed-loop control (active feedback) methods for the active monitoring of the electrochemical etching parameters during etching of semiconductor materials and to actively adjust other electrochemical etching parameters, wherein said adjustment is based on the results of said monitoring in order to produce porous semiconductor structures with well controlled parameters (such as pore sizes, morphology or porosity) throughout the entire depth of said porous semiconductor layers.
The present exemplary illustrative non-limiting implementations provide said closed-loop control for different types of semiconductors (e.g., Si, Ge, III-V compound semiconductors) and for different levels and types of doping of said semiconductors. Control over the semiconductor electrochemical etching process can be realized by:                measuring the present value of the resistivity (or conductivity) of the electrochemical system composed of the semiconductor wafer (anode), electrolyte and cathode electrode; and/or        adjusting the electrochemical etching parameters according to the detected changes in said value of the resistivity (or conductivity) of said electrochemical system occurring during the electrochemical etching process at least once.Said electrochemical etching parameters that can be adjusted include, but are not limited to, the applied current density, the time constant of electrical current modulation, the amplitude of said current modulation and the temperature of the electrolyte. The said time constant of electrical current modulation is particularly important if any type of multilayer structure is to be formed. Said semiconductor wafer can be a p-doped, (100)-oriented, single-crystal silicon wafer with resistivity in the range of 1 and 1000 Ωcm, said electrolyte can be an HF (hydrofluoric acid)-based electrolyte and said electrochemical etching can be done in the galvanostatic mode (or, in other words, in the current-control mode, when the applied current at any given point of time is set to some value, and the applied voltage is changing to any value needed to achieve said value of applied current). Said porous layer in this case will be macroporous silicon layer and said current modulation can be used to coherently modulate the diameters of said macropores. Said resistivity (or conductivity) measurements can be performed by setting a certain value of current density (in relation to the active area of the semiconductor wafer), recording the voltage needed to achieve said current density, dividing the current density into the voltage, comparing the obtained resistance density number with the stored value either obtained at the beginning of the electrochemical process or determined during calibration runs, and subsequently adjusting an electrochemical etching parameter. The time constant of current modulation can be taken as a nonlimiting example of said parameter adjustment. Alternatively, said semiconductor wafer can be p-doped, (111)-oriented single-crystal silicon wafer with a resistivity in the range of 1 to 1000 Ωcm, said electrolyte can be an HF (hydrofluoric acid)-based electrolyte and said electrochemical etching can be accomplished in the galvanostatic mode. Said porous layer in this case will be a macroporous silicon layer and said current modulation can be used to coherently switch the morphology of said macropores (between current-oriented pores and crystallographically-oriented pores). Alternatively, said semiconductor wafer can be a p-doped or an n-doped (100)- or (111)-oriented single-crystal wafer of a III-V compound semiconductor (for example, InP, GaAs or GaP) with doping density in the range of 1016-1018 cm−3, said electrolyte can be an acidic electrolyte and said electrochemical etching can be done in the galvanostatic or potentiostatic modes. Said porous layer in this case will be a macroporous semiconductor layer and said current modulation can be used to modulate either the diameters of the macropores or the morphology of the porous layer (switching the morphology between current-oriented pores and crystallographically-oriented pores). In the latter case either the time constant of the current modulation can be adjusted according to resistivity (or conductivity) measurements or the mode of electrochemical etching can be switched between the potentiostatic and galvanostatic modes. Alternatively, said semiconductor wafer can be a p-doped or n-doped (100)- or (111)-oriented single-crystal silicon wafer with resistivity in the range of 1 to 999 mΩcm, said electrolyte can be an HF (hydrofluoric acid)-based electrolyte and said electrochemical etching can be done in the galvanostatic mode. Said porous layer in this case will be a mesoporous silicon layer and said current modulation can be used to modulate the porosity of the porous layer.        
According to a second exemplary illustrative non-limiting implementation, closed-loop control over the semiconductor electrochemical etching process can be realized by:                determining the frequency of self-induced voltage oscillations of a system consisting of a semiconductor wafer (anode), an electrolyte bath in contact with the first surface of said wafer, a counter electrode (cathode) in contact with the electrolyte bath opposite to said wafer, said system being operated in the galvanostatic mode at least during said determination procedure of said frequency.        adjusting the electrochemical etching parameters according to the detected changes in said frequency of said self-oscillations of said electrochemical system, as occur during the electrochemical etching process.Said electrochemical etching parameters that can be adjusted include, but are not limited to, the applied current density, the time constant of current modulation (if a multilayer structure of alternating or varying porosities is to be formed in said semiconductor wafer, amplitude of said current modulation, and the temperature of the electrolyte(s). Said semiconductor wafer can be a p-doped, (100)-oriented single-crystal silicon wafer with resistivity in the range of 1 and 1000 Ωcm and said electrolyte can be an HF (hydrofluoric acid)-based electrolyte. Said porous layer in this case will be a macroporous silicon layer and said current modulation can be used to coherently modulate the diameters of said macropores. Said measurements of frequency of voltage self-oscillations (which is typically in the range of 1 mHz to 100 Hz) can be performed by setting a certain value of current density, recording the temporal dependence of the voltage needed to achieve said current density over at least the time equal to several periods of said voltage self oscillations, and mathematically processing said recorded data in order to extract said self-oscillation frequency and phase. As a nonlimiting example of said current-modulated electrochemical process, said frequency can be recorded at least once during each cycle of current modulation and the electrochemical etching parameters (such as amplitude of said current modulation, or frequency of said current modulation) can be adjusted according to the detected changes to the measured frequency of said voltage self-oscillations. According to a further aspect of the second exemplary illustrative non-limiting implementation, said frequency of the voltage self-oscillations of the electrochemical system consisting of the semiconductor wafer as one electrode, a counter electrode, and with electrolyte between them, can be determined by adding a small perturbation to the applied current (in the galvanostatic mode) and scanning the frequency of said perturbation signal within some frequency range, and further detecting the amplitude and/or the phase of the recorded voltage response of said electrochemical system. The range of scanned frequencies can be either near the main frequency of said voltage self-oscillations or near some of the higher harmonics of said frequency. Detection of the frequency and/or phase of the response around higher harmonics can be more convenient from instrumental point of view since the main frequency of self-oscillations can be quite low for certain combinations of semiconductor wafers and electrolytes, for instance, in the mHz range. Alternatively, said semiconductor wafer can be a p-doped, (111)-oriented single-crystal silicon wafer with resistivity in the range of 1 to 1000 Ωcm, said electrolyte can be an HF (hydrofluoric acid)-based electrolyte and said electrochemical etching can be performed in the galvanostatic mode. Said porous layer in this case will be a macroporous silicon layer, and said current modulation can be used to coherently switch the morphology of said macropores between current-oriented pores (i.e., pores are directed along the current lines, typically perpendicular to the wafer surface) and crystallographically-oriented pores (i.e., pores directed along some preferred crystallographic directions, often at some angle with respect to the wafer surface). Alternatively, said semiconductor wafer can be a p-doped or an n-doped (100)- or (111)-oriented single-crystal wafer of III-V compound semiconductor (for example, InP, GaAs or GaP) with doping density in the range of 5×1015-5×1018 cm−3, said electrolyte can be an acidic electrolyte and said electrochemical etching can be performed in the galvanostatic and/or potentiostatic modes. Said porous layer in this case will be a macroporous semiconductor layer, and said current modulation can be used to modulate either the diameters of the macropores or the morphology of the porous layer, again switching the morphology between current-oriented pores and crystallographically-oriented pores. In the latter case, either the time constant of the current modulation can be adjusted according to self-oscillation frequency measurements or the electrochemical etching can be switched between the potentiostatic and galvanostatic modes.        
According to a third exemplary illustrative non-limiting implementation, closed-loop control over the semiconductor electrochemical etching process can be realized by                recording the IV (current-voltage) curve such that the process of IV curve acquisition is much faster than the overall electrochemical etching process time,        applying signal processing in order to extract the current and voltage values at the Jps peak contained in the recorded IV curve, and        adjusting the electrochemical etching parameters according to the detected changes in said values of voltage and current that occur at the Jps peak during the electrochemical etching process.        
Said electrochemical etching parameters that can be adjusted include, but not limited to, the applied current density, illumination intensity, time constant of current, voltage and/or illumination intensity modulation (if porosity multilayer is to be formed in said semiconductor wafer), amplitude of said current, voltage and/or illumination intensity modulation, temperature of the electrolyte. Said semiconductor wafer can be n-doped (100)-oriented single-crystal silicon wafer with resistivity in the range of 0.1 to 100 Ωcm, said electrolyte can be an HF (hydrofluoric acid)-based electrolyte and said electrochemical etching can be accomplished in the potentiostatic mode. Said porous layer in this case will be a macroporous silicon layer and said current modulation required for said coherent modulation of macropore diameters can be achieved by means of temporal modulations of illumination intensity and/or applied voltage. Said IV curve measurements can be performed then as follows: The illumination intensity can be fixed at some reasonably high value during the measurements and the applied voltage can be scanned while recoding the resultant current flowing through the system. It is essential in such measurements that the voltage scan rate (and the overall measurement time) is fast enough not to cause a disturbance in the pore growth. If the illumination intensity was set to high enough value and the silicon wafer is of good enough quality (i.e. the minor carrier diffusion length is high enough), the IV curve will then contain a pronounced peak, which is known as Jps peak. It's voltage and current positions can be determined by an appropriate mathematical algorithm, which can include, as a nonlimiting example, polynomial or other non-physical (purely mathematical) curve fitting, or, as a second nonlimiting example, fitting with a physically-based theory. The determined values of the voltage and current positions of the Jps peak then can be compared to the reference values (which could be either obtained at the beginning of the process or can be preliminarily determined through calibration runs), and the electrochemical process parameters can then be adjusted accordingly. Said electrochemical etching parameters that can be adjusted include but not limited to the time constant of current modulation by means of varying the time constant of the illumination intensity modulation and/or applied voltage modulation, the amplitude of illumination intensity and the amplitude of applied voltage. Alternatively, said semiconductor wafer can be a p-doped or an n-doped (100)- or (111)-oriented single-crystal wafer of III-V compound semiconductor (for example, InP, GaAs or GaP) with doping density in the range of 1016-1018 cm−3. Said electrolyte can be an acidic electrolyte and said electrochemical etching can be done in the galvanostatic or potentiostatic mode. In the latter case, said IV curve can be obtained in a potentiostatic mode with or without back- or front-side illumination by simply scanning the voltage and recording the values of the current and subsequently applying signal processing and electrochemical parameter adjustment, as previously described. The time of IV testing must be carefully optimized in this case since it may cause considerable effect on the results. Dependence of the IV curve shape on a speed of scanning was observed if said speed of scanning is below some characteristic response time of the system, which varies is a wide range for different semiconductor material/electrolyte combinations and typically is in the range of several seconds. The time of IV curve recording should be slower, though, than the characteristic etching process time in order not to interfere with the pore growth.